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| Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 DESCRIPTION The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL(R) device. Combining versatile output macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic. The use of Philips Semiconductors state-of-the-art bipolar oxide isolation process enables the 10H20EV8/10020EV8 to achieve optimum speed in any design. The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations. The 10H20EV8/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or 12th input, 90 AND gates, and 8 Output Logic Macrocells. Each Output Macrocell can be individually configured as a dedicated input, dedicated output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback to the AND array. This gives the part the capability of having up to 20 inputs and eight outputs. The 10H20EV8/10020EV8 has a variable number of product terms that can be OR'd per output. Four of the outputs have 12 AND terms available and the other four have 8 terms per output. This allows the designer the extra flexibility to implement those functions that he couldn't in a standard PAL device. Asynchronous Preset and Reset product terms are also included for system design ease. Each output has a separate output enable product term. Another feature added for the system designer is a power-up Reset on all registered outputs. The 10H20EV8/10020EV8 also features the ability to Preload the registers to any desired state during testing. The Preload is not affected by the pattern within the device, so can be performed at any step in the testing sequence. This permits full logical verification even after the device has been patterned. PIN CONFIGURATIONS F Package I1 1 I2 2 CLK/I12 3 F1 4 24 VCC 23 I11 22 I10 21 F8 20 F7 19 VCO2 18 F6 17 F5 16 I9 15 I8 14 I7 13 I6 FEATURES * Ultra high speed ECL device - tPD = 4.5ns (max) - tIS = 2.6ns (max) - tCKO = 2.3ns (max) - fMAX = 208MHz F2 5 VCO1 6 F3 7 F4 8 I3 9 I4 10 I5 11 VEE 12 F = Ceramic DIP (300mil-wide) * Universal ECL Programmable Array Logic - 8 user programmable output macrocells - Up to 20 inputs and 8 outputs - Individual user programmable output polarity * Variable product term distribution allows increased design capability A Package CLK/I12 I2 4 F1 5 F2 6 VCO1 7 NC 8 F3 9 F4 10 I3 11 12 I4 13 14 15 16 17 I7 18 I8 I5 VEE NC I6 3 I1 NC VCC I11 I10 2 1 28 27 26 25 F8 24 F7 23 VCO2 22 NC 21 F 6 20 F5 19 I9 * Asynchronous Preset and Reset capability * 10KH and 100K options * Power-up Reset and Preload function to enhance state machine design and testing * Design support provided via SNAP and other CAD tools * Security fuse for preventing design duplication * Available in 24-Pin 300mil-wide DIP and 28-Pin PLCC. A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION 24-Pin Ceramic Dual In-Line (300mil-wide) 28-Pin Plastic Leaded Chip Carrier ORDER CODE 10H20EV8-4F 10020EV8-4F 10H20EV8-4A 10020EV8-4A DRAWING NUMBER 0586B 0401F (R)PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc. October 22, 1993 113 853-1423 11164 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 LOGIC DIAGRAM 3 0 D 0 OUTPUT LOGIC MACRO CELL 4 4 8 12 INPUT LINES 16 20 24 28 32 36 7 D 0 OUTPUT LOGIC MACRO CELL 21 7 1 D 0 11 2 D 0 OUTPUT LOGIC MACRO CELL 5 11 9 D 0 OUTPUT LOGIC MACRO CELL 20 11 10 D 0 OUTPUT LOGIC MACRO CELL 7 11 11 D 0 OUTPUT LOGIC MACRO CELL 18 7 OUTPUT LOGIC MACRO CELL 8 13 D 0 OUTPUT LOGIC MACRO CELL 17 7 14 15 16 23 22 ASYNCHRONOUS RESET ASYNCHRONOUS PRESET NOTES: 1. All unprogrammed or virgin "AND" gate locations are pulled to logic "0" 2. Programmable connections 3. Pinout for F Package October 22, 1993 114 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 FUNCTIONAL DIAGRAM CLK/I I 1 11 PROGRAMMABLE AND ARRAY (90 x 40) 12 12 8 8 8 8 12 12 RESET OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL OUTPUT LOGIC MACROCELL PRESET F F F F F F F F FUNCTIONAL DESCRIPTION The 10H20EV8/10020EV8 is an ultra high-speed universal ECL PAL-type device. Combining versatile Output Macrocells with a standard AND/OR single programmable array, this device is ideal in implementing a user's custom logic. As can be seen in the Logic Diagram, the device is a two-level logic element with a programmable AND array. The 20EV8 can have up to 20 inputs and 8 outputs. Each output has a versatile Macrocell whereby the output can either be configured as a dedicated input, a dedicated combinatorial output with polarity control, a bidirectional I/O, or as a registered output that has both output polarity control and feedback into the AND array. The device also features 90 product terms. Two of the product terms can be used for a global asynchronous preset and/or reset. Eight of the product terms can be used for individual output enable control of each Macrocell. The other 80 product terms are distributed among the outputs. Four of the outputs have eight product terms, while the other four have 12. This arrangement allows the utmost in flexibility when implementing user patterns. Output Logic Macrocell The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs. As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S0 and S1 allow the user to select between the various cells. S1 controls whether the output will be either registered with internal feedback or combinatorial I/O. S0 controls the polarity of the output (ActiveHIGH or Active-LOW). This allows the user to achieve the following configurations: Registered Active-HIGH output, Registered Active-LOW output, Combinatorial ActiveHIGH output, and Combinatorial Active-LOW output. With the output enable product term, this list can be extended by adding the configurations of a Combinatorial I/O with Polarity or another input. Fn AP D Q OUTPUT SELECT MUX S1 S0 CLK AR Q VCC FEEDBACK MUX VCC S1 Figure 1. Output Logic Macrocell October 22, 1993 115 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 ABSOLUTE MAXIMUM RATINGS1 SYMBOL VEE VIN IO TS TJ Supply voltage Input voltage (VIN should never be more negative than VEE) Output source current Operating Temperature range Storage Temperature range Ceramic Package Plastic Package PARAMETER RATING -8.0 0 to VEE -50 -55 to +150 +165 +150 UNIT V V mA C C C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. DC OPERATING CONDITIONS 10H20EV8 TEST SYMBOL VCC, VCO1, VCO2 VEE Circuit ground Supply voltage (negative) Tamb = 0C VIH High level input voltage Tamb = +25C Tamb = +75C Tamb = 0C VIL Low level input voltage Tamb = +25C Tamb = +75C Tamb Operating ambient temperature range -1170 -1130 -1070 -1950 -1950 -1980 0 +25 PARAMETER CONDITIONS MIN 0 LIMITS NOM 0 -5.2 -840 -810 -735 -1480 -1480 -1450 +75 MAX 0 UNIT V V mV mV mV mV mV mV C NOTE: When operating at other than the specified VEE voltage (-5.2V), the DC and AC Electrical Characteristics will vary slightly from specified values. DC OPERATING CONDITIONS 10020EV8 TEST SYMBOL VCC, VCO1, VCO2 VEE VEE Circuit ground Supply voltage Supply voltage when opetating with the 10K or 10KH ECL family VEE = -4.2V VIH High level input voltage VEE = -4.5V VEE = -4.8V VEE = -4.2V VIL Low level input voltage VEE = -4.5V VEE = -4.8V Tamb Operating ambient temperature range 0 +25 -1810 PARAMETER CONDITIONS MIN 0 -4.8 -5.7 -1150 -1165 -1165 -1475 -1475 -1490 +85 mV mV mV C -880 mV LIMITS NOM 0 -4.5 MAX 0 -4.2 UNIT V V V NOTE: When operating at other than the specified VEE voltages (-4.2V, -4.5V, -4.8V), the DC and AC Electrical Characteristics will vary slightly from their specified values. October 22, 1993 116 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 D AP D AP D Q D Q CK Q AR CK Q AR Registered Active-HIGH Registered Active-LOW D D Combinatorial Active-HIGH Figure 2. Combinatorial Active-LOW Output Macro Cell Configurations Active-HIGH and Active-LOW, a Preset signal will force the Active-HIGH outputs HIGH while the Active-LOW outputs would go LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions. OUTPUT MACRO CELL CONFIGURATION Shown in Figure 2 are the four possible configurations of the output macrocell using fuses S0 and S1. As seen, the output can either be registered Active-HIGH/LOW with feedback or combinatorial Active-HIGH/LOW with feedback. If the registered mode is chosen, the feedback from the Q output to the AND array enables one to make state machines or shift registers without having to tie the output to one of the inputs. If a combinatorial output is chosen, the feedback gate is enabled from the pin and allows one to create permanent outputs, permanent inputs, or I/O pins through the use of the output enable (D) product term. controlled by a programmed pattern. A HIGH on the D term enables the output, while a LOW performs the disable function. Output enable control can be achieved by programming a pattern on the D term. The output enable control can also be used to expand a designer's possibilities once a combinatorial output has been chosen. If the D term is always HIGH, the pin becomes a permanent Active-HIGH/LOW output. If the D term is always LOW (all fuses left intact), the pin now becomes an extra input. PRELOAD To simplify testing, the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the PRELOAD can be done on a blank part and after that same part has been programmed to facilitate any post-fuse testing desired. It can also be used by a designer to help debug a circuit. This could be important if a state machine was implemented in the 10H20EV8/ 10020EV8. The PRELOAD would allow the entry of any state in the sequence desired and start clocking from that particular point. Any or all transitions could be verified. PRESET AND RESET The 10H20EV8/10020EV8 also includes a separate product term for asynchronous Preset and asynchronous Reset. These lines are common for all registers and are asserted when the specific product term goes HIGH. Being asynchronous, they are independent of the clock. It should be noted that the actual state of the output is dependent on how the polarity of the particular output has been chosen. If the outputs are a mix of OUTPUT ENABLE Each output on the 10H20EV8/10020EV8 has its own individual product term for output enable. The use of the D product term (direction control) allows the user three possible configurations of the outputs. They are: always enabled, always disabled, and October 22, 1993 117 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 DC ELECTRICAL CHARACTERISTICS 10H20EV8 0C Tamb +75C, VEE = -5.2V 5%, VCC = VCO1 = VCO2 = GND LIMITS4 SYMBOL VOH PARAMETER1 High level output voltage TEST CONDITIONS2 VIN = VIH MIN or VIL MAX Tamb 0C +25C +75C 0C +25C +75C 0C +75C 0C +75C 0C to +75C 250 mA 0.3 MIN -1020 -980 -920 -1950 -1950 -1950 MAX -840 -810 -735 -1630 -1630 -1600 220 UNITS mV VOL Low level output voltage VIN = VIH MIN or VIL MAX mV IIH IIL -IEE High level input current Low level input current Supply current VIN = VIH MAX VIN = VIL MIN Except I/O Pins VEE = MAX All inputs = VIH MAX A A DC ELECTRICAL CHARACTERISTICS 10020EV8 0C Tamb +85C, -4.8V VEE -4.2V, VCC = VCO1 = VCO2 = GND LIMITS4 SYMBOL PARAMETER1 TEST CONDITIONS2 VEE = -4.2V VOH High level output voltage VIN = VIH MAX or VIL MIN VEE = -4.5V VEE = -4.8V Outputs VOHT High level output threshold voltage Loaded with 50 to -2.0V VOLT Low level output threshold voltage 0.010V Apply VIHMIN or VILMAX to one input at a time, other inuts at VIHMAX or VILMIN. Apply VIHMIN or VILMAX to one input at a time, other inuts at VIHMAX or VILMIN. VEE = -4.2V VEE = -4.5V VEE = -4.8V VEE = -4.2V VEE = -4.5V VEE = -4.8V VEE = -4.2V VOL Low level output voltage Inuts at VIHMAX or VILMIN. VEE = -4.5V VEE = -4.8V IIH IIL -IEE High level input current Low level input current VEE supply current One input under test at VIHMAX. Other inputs at VILMIN. One input under test at VILMIN. Other inputs at VIHMAX. All inputs at VIHMAX. 0.5 230 -1810 -1810 -1830 -1705 MIN -1020 -1025 -1035 -1030 -1035 -1045 -1595 -1610 -1610 -1605 -1620 -1620 220 -955 TYP MAX -870 -880 -880 UNITS mV mV mV mV mV mV mV mV mV mV mV mV A A mA NOTES: 1. All voltage measurements are referenced to the ground terminal. 2. Each ECL 10KH/100K series device has been designed to meet the DC specification after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least 2 minutes, while maintaining transverse airflow of 2.5 meters/sec (500 linear feet/min.) over the device, mounted either in a test socket or on a printed circuit board. Test voltage values are given in the DC operating conditions table. Conditions for testing shown in the tables are not necessarily worst case. For worst case testing guidelines, refer to DC Testing, Chapter 1, Section 3, of the Philips Semiconductors 10/100K ECL Data Handbook. 3. Terminals not specifically referenced can be left electrically open. Open inputs assume a logic LOW state. Any unused pins can be terminated to -2V. If tied to VEE, it must be through a resistor > 10K. It is recommended that pins that have been programmed as RESET, PRESET, or CLOCK inputs not be left open due to the possibility of false triggering from internally and externally generated switching transients. 4. The specified limits represent the worst case values for the parameter. Since these worst case values normally occur at the supply voltage and temperature extremes, additional noise immunity can be achieved by decreasing the allowable operating condition ranges. October 22, 1993 118 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 AC ELECTRICAL CHARACTERISTICS (for Ceramic Dual In-Line Package) 10H20EV8: 0C Tamb +75C, VEE = -5.2V 5%, VCC = VCO1 = VCO2 = GND 10020EV8: 0C Tamb +85C, -4.8V VEE -4.2V, VCC = VCO1 = VCO2 = GND LIMITS1 SYMBOL PARAMETER FROM TO MIN2 Pulse Width tCKH tCKL tCKP tPRH Clock High Clock Low Clock Period Preset/Reset Pulse CLK + CLK - CLK + (I, I/O) CLK - CLK + CLK + (I, I/O) 2.0 2.0 4.0 4.5 -- 0.6 0.9 2.0 2.0 4.0 4.5 -- 0.6 0.9 2.0 2.0 4.0 4.5 -- 0.6 0.9 ns ns ns ns 0C TYP3 MAX 2 +25C MIN2 TYP3 MAX 2 +75C/+85C MIN2 TYP3 MAX 2 UNIT Setup and Hold Time tIS tIH tPRS Input Input Clock Resume after Preset/Reset (I, I/O) CLK + (I, I/O) CLK + (I, I/O) CLK + 2.6 0.1 4.6 1.0 <0 1.0 2.6 0.1 4.6 1.1 <0 0.9 2.7 0.1 4.6 1.4 <0 0.8 ns ns ns Propagation Delay tPD tCKO tOE tOD tPRO tPPR fMAX Input Clock Output Enable Output Disable Preset/Reset Power-on Reset (I, I/O) CLK + (I, I/O) (I, I/O) (I, I/O) VEE I/O I/O I/O I/O I/O I/O 212 2.85 1.65 2.0 2.0 2.8 -- 377 4.7 2.4 4.2 4.2 4.7 10 212 2.95 1.7 2.1 2.1 3.0 -- 357 4.7 2.4 4.2 4.2 4.7 10 204 3.35 2.0 2.2 2.2 3.5 -- 294 4.7 2.5 4.2 4.2 4.7 10 ns ns ns ns ns ns MHz NOTES: 1. Refer to AC Test Circuit and Voltage Wafeforms diagrams. 2. Maximum loading conditions: 89 fuses intact per row. 3. Typical loading conditions: 15 fuses intact per row. (All "inactive" fuses, except those necessary for correct functionality, are removed.) October 22, 1993 119 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier) 10H20EV8: 0C Tamb +75C, VEE = -5.2V 5%, VCC = VCO1 = VCO2 = GND 10020EV8: 0C Tamb +85C, -4.8V VEE -4.2V, VCC = VCO1 = VCO2 = GND LIMITS1 SYMBOL PARAMETER FROM TO MIN Pulse Width tCKH tCKL tCKP tPRH Clock High Clock Low Clock Period Preset/Reset Pulse CLK + CLK - CLK + (I, I/O) CLK - CLK + CLK + (I, I/O) 2.0 2.0 4.0 4.5 -- 0.6 0.9 2.0 2.0 4.0 4.5 -- 0.6 0.9 2.0 2.0 4.0 4.5 -- 0.6 0.9 ns ns ns ns 0C TYP3 MAX 2 +25C MIN TYP3 MAX 2 +75C/+85C MIN TYP3 MAX 2 UNIT Setup and Hold Time tIS tIH tPRS Input Input Clock Resume after Preset/Reset (I, I/O) CLK + (I, I/O) CLK + (I, I/O) CLK + 2.5 0 4.5 1.0 <0 1.0 2.5 0 4.5 1.1 <0 0.9 2.6 0 4.5 1.4 <0 0.8 ns ns ns Propagation Delay tPD tCKO tOE tOD tPRO tPPR fMAX Input Clock Output Enable Output Disable Preset/Reset Power-on Reset (I, I/O) CLK + (I, I/O) (I, I/O) (I, I/O) VEE I/O I/O I/O I/O I/O I/O 212 2.85 1.65 2.0 2.0 2.8 -- 377 4.5 2.2 4.0 4.0 4.5 10 212 2.95 1.7 2.1 2.1 3.0 -- 357 4.5 2.2 4.0 4.0 4.5 10 204 3.35 2.0 2.2 2.2 3.5 -- 294 4.5 2.3 4.0 4.0 4.5 10 ns ns ns ns ns ns MHz NOTES: 1. Refer to AC Test Circuit and Voltage Wafeforms diagrams. 2. Maximum loading conditions: 89 fuses intact per row. 3. Typical loading conditions: 15 fuses intact per row. (All "inactive" fuses, except those necessary for correct functionality, are removed.) October 22, 1993 120 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 AC TEST CIRCUIT +2.0V + 0.010V 25F 0.1F L1 PULSE GENERATOR L3 VCO1 I1 VCC VCO2 FX L2 SCOPE CL RT I11 SCOPE RT CLK/I12 FM DUT FY FN VEE 25F 0.01F -2.5V + 0.010V FOR 10020EV8 -3.2V + 0.010V FOR 10H20EV8 NOTES: 1. Use decoupling capacitors of 0.1F and 25F from GND to VCC, and 0.01F and 25F from GND to VEE (0.01 and 0.1F capacitors should be NPO Ceramic or MLC type). Decoupling capacitors should be placed as close as physically possible to the DUT and lead length should be kept to less than 1/4 inch (6mm). 2. All unused inputs should be connected to either HIGH or LOW state consistent with the LOGIC function required. 3. All unused outputs are loaded with 50 to GND. 4. L1 and L2 are equal length 50 impedance lines. L3, the distance from the DUT pin to the junction of the cable from the Pulse Generator and the cable to the Scope, should not exceed 1/4 inch (6mm). 5. RT = 50 terminator internal to Scope. 6. The unmatched wire stub between coaxial cable and pins under test must be less than 1/4 inch (6mm) long for proper test. 7. CL = Fixture and stray capacitance 3pF. 8. Any unterminated stubs connected anywhere along the transmission line between the Pulse Generator and the DUT or between the DUT and the Scope should not exceed 1/4 inch (6mm) in length (refer to section on AC setup procedure). 9. All 50 resistors should have tolerance of 1% or better. 10. Test procedures are shown for only one input or set of input conditions. Other inputs are tested in the same manner. October 22, 1993 121 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 VOLTAGE WAVEFORMS tTHL tTLH +1110mV (10H20EV8) +1050mV (10020EV8) NEGATIVE PULSE 80% 50% 20% tW(L) tW(H) 20% 80% 50% +310mV POSITIVE PULSE 80% 50% 20% 80% 50% 20% +1110mV (10H20EV8) +1050mV (10020EV8) +310mV tTLH tTHL INPUT PULSE REQUIREMENTS VCC = VCO1 = VCO2 = +2.0V +0.010V, VEE = -3.2V + 0.010V, VT = GND (0V) FAMILY 10KH ECL AMPLITUDE 800mVP-P REP RATE 1MHz PULSE WIDTH 500ns tTLH 1.3 + 0.2ns tTHL 1.3 + 0.2ns INPUT PULSE REQUIREMENTS VCC = VCO1 = VCO2 = +2.0V +0.010V, VEE = -2.5V + 0.010V, VT = GND (0V) FAMILY 100K ECL AMPLITUDE 740mVP-P REP RATE 1MHz PULSE WIDTH 500ns tTLH 0.7 + 0.1ns tTHL 0.7 + 0.1ns Input Pulse Definition October 22, 1993 122 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 TIMING DIAGRAMS I, I/O (INPUT) 50% 50% tIH tIS 50% CLK tCKH tCKO I/O (REGISTERED OUTPUT) 50% 50% tCK tCKL P 50% tPD I/O (COMBINATORIAL OUTPUT) 50% Flip-Flop and Gate Outputs 0V VEE = -4.94 10H20EV8 VEE = -4.2 10020EV8 VEE tPPR REGISTERED ACTIVE-LOW OUTPUT I, I/O (INPUT) 50% tIS tCLK 50% 50% Power-On Reset October 22, 1993 123 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 TIMING DIAGRAMS (Continued) I, I/O (INPUT) 50% 50% tOD tOE I/O (OUTPUT) 50% 50% Output Enable/Disable 50% CLK tPRS ASYNCHRONOUS PRESET/RESET 50% 50% tPRH tPRO I/O (OUTPUT) 50% Asynchronous Preset/Reset October 22, 1993 124 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 REGISTER PRELOAD The 10H20EV8/10020EV8 has included circuitry that allows a user to load data into the output registers. Register PRELOAD can be done at any time and is not dependent on any particular pattern programmed into the device. This simplifies the ability to fully verify logic states and sequences even after the device has been patterned. The pin levels and sequence necessary to perform the register PRELOAD are shown below. PIN 3 VIH VPP PIN 23 VOH OUTPUTS VIH VOL VIL APPLY EXTERNAL INPUTS TO BE PRELOADED DATA PRELOADED AND PRELOAD DISABLED REMOVE EXTERNAL INPUTS DISABLE OUTPUTS ENABLE PRELOAD LIMITS SYMBOL VIH VIL VPP PARAMETER Input HIGH level during PRELOAD and Verify Input LOW level during PRELOAD and Verify PRELOAD enable voltage applied to I11 MIN -1.1 -1.85 1.45 TYP -0.9 -1.65 1.6 MAX -0.7 -1.45 1.75 UNIT V V V NOTE: 1. Unused inputs should be handled as follows: - Set at VIH or VIL - Terminated to -2V - Tied to VEE through a resistor > 10K - Open October 22, 1993 125 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 LOGIC PROGRAMMING The 10H20EV8/10020EV8 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABELTM and CUPLTM design software packages also support the 10H20EV8/10020EV8. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. 10H20EV8/10020EV8 logic designs can also be generated using the program table entry format detailed on the following page. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, F, Q, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. "AND" ARRAY - (I), (F), (Qp) I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q I, F, Q P, D, AP, AR STATE INACTIVE1, 2 CODE O STATE I, F, Q P, D, AP, AR CODE H STATE I, F, Q P, D, AP, AR CODE L STATE P, D, AP, AR CODE - DON'T CARE NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates. 2. Any gate (P, D, AP, AR) will be unconditionally inhibited if any one of the I, F or Q link pairs is left intact. OUTPUT MACROCELL CONFIGURATIONS OUTPUT MACROCELL CONFIGURATION Registered Output, Active-HIGH Registered Output, Active-LOW Combinatorial I/O, Active-HIGH Combinatorial I/O, Acitve-LOW NOTE: 1. This is the initial (unprogrammed) state of the device. CONTROL WORD FUSE D D1 B B POLARITY FUSE H L1 H L PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of the 1992 PLD Data Handbook for additional information. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 126 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 PROGRAM TABLE CONTROL WORD T E R M 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 AR AP PIN VARIABLE NAME AND I 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 F(I) 54 3 2 1 8 7 POLARITY OR (FIXED) F(O) 6543 2 1 D A A A A A A A A D A A A A A A A A D A A A A A A A A A A A A D A A A A A A A A A A A A D A A A A A A A A A A A A D A A A A A A A A A A A A D A A A A A A A A D A A A A A A A A 3 23 22 16 15 14 13 11 10 9 2 1 21 20 18 17 8 7 5 4 October 22, 1993 127 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 SNAP Features * JEDEC fuse map generated from netlist SNAP (Synthesis, Netlist, Analysis and Program) is a versatile development tool that speeds the design and testing of PML. SNAP combines a user-friendly environment and powerful modules that make designing with PML simple. The SNAP environment gives the user the freedom to design independent of the device architecture. The flexibility in the variations of design entry methodologies allows design entry in the most appropriate terms. SNAP merges the inputs, regardless of the type, into a highlevel netlist for simulation or compilation into a JEDEC fuse map. The JEDEC fuse map can then be transferred from the host computer to the device programer. * Schematic entry using DASHTM 4.0 or above or OrCADTM SDT III * State Equation Entry * Boolean Equation Entry * Allows design entry in any combination of above formats SNAP's simulator uses a synthetic logic analyzer format to display and set the nodes of the design. The SNAP simulator provides complete timing information, setup and hold-time checking, plus toggle and fault grading analysis. SNAP operates on an IBM(R) PC/XT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk. * Simulator - Logic and fault simulation - Timing model generation for device timing simulation - Synthetic logic analyzer format DESIGN SECURITY The 10H20EV8/10020EV8 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. * Macro library for standard TTL and user defined functions * Device independent netlist generation October 22, 1993 128 Philips Semiconductors Programmable Logic Devices Product specification ECL programmable array logic 10H20EV8/10020EV8 SNAP RESOURCE SUMMARY DESIGNATIONS CLK/I CKEV8 1 11 I NINEV8 DINEV8 NINEV8 DINEV8 PROGRAMMABLE AND ARRAY (90 x 40) DINEV8 NINEV8 DINEV8 NINEV8 DINEV8 NINEV8 DINEV8 NINEV8 DINEV8 NINEV8 DINEV8 NINEV8 12 12 8 8 8 8 AND DINEV8 NINEV8 DINEV8 NINEV8 12 12 OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL OR OUTPUT LOGIC MACROCELL RESET CLK PRESET DFFEV8, OLMDIR, OLMINV, OLMREG OUTEV8 OUTEV8 OUTEV8 OUTEV8 OUTEV8 OUTEV8 OUTEV8 OUTEV8 F F F F F F F F OUTEV8 Fn AP D Q OLMREG CLK AR Q OUTPUT SELECT MUX S1 S0 VCC OLMDIR OLMINV FEEDBACK MUX VCC S1 Output Logic Macrocell October 22, 1993 129 |
Price & Availability of 10H20EV8
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